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MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512 X 9 PARALLEL SYNCHRONOUS FIFO, MONOLITHIC SILICON

contributor authorDLA - CC - DLA Land and Maritime
date accessioned2017-09-04T18:32:06Z
date available2017-09-04T18:32:06Z
date copyright05/09/2006
date issued2006
identifier otherJANDJBAAAAAAAAAA.pdf
identifier urihttp://mapnamagz.yabesh.ir/std;query=autho1826AF67FCdardstandardsfen/handle/yse/214315
description abstractScope:

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
Intended Use: Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.

languageEnglish
titleSMD-5962-93249 REV Bnum
titleMICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512 X 9 PARALLEL SYNCHRONOUS FIFO, MONOLITHIC SILICONen
typestandard
page26
statusActive
treeDLA - CC - DLA Land and Maritime:;2006
contenttypefulltext


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